1. Technical Field
The present invention generally relates to a comparator, and more particularly, to a dynamic comparator with background offset calibration.
2. Background
Comparator based analog-to-digital converters (ADCs), such as successive approximation registers (SARs), flash ADCs, folding ADCs, and sub-ranging ADCs, has always been the focus of ADC research. A comparator based ADC requires no operational amplifier (OPAMP), and therefore offers relatively high integrity, especially when it is applied in a deep-submicron fabrication process (<0.13 um).
In addition, the comparators in many high-speed (>GSample/second (GS/s in short)) ADCs adopt a dynamic structure so that quiescent current consumption is avoided. Moreover, the power consumption of a comparator based ADC can be greatly reduced, and accordingly, the design of OPAMP based pipelined ADC has been converted into comparator based ADC in recent years. Thereby, comparator based ADC has become one of the major techniques developed in related fields, and how to make a comparator based ADC have a high speed, (>GS/s), a low power consumption, and a medium/high resolution (≧8 bits) has become a major subject in the related fields.
Many comparator structures that offer high speed and low power consumption have been developed. The most representative one among foregoing structures is disclosed in the article titled “A current controlled latch sense amplifier and a static power-saving input buffer for low-power architecture” published by Kobayashi in 1993 (IEEE JSSC). The most representative comparator structure that offers a medium/high resolution is disclosed in the article titled “Design techniques for high-speed, high-resolution comparators” published by Razavi in 1992 (IEEE JSSC).
Researches done after year 2000 show that the dynamic comparator structure provided by Kobayashi can fulfil the requirements of both high speed and low power consumption if the sampling frequency of the comparator based ADC is set to be greater than GS/s. Thus, this structure has become the most commonly adopted comparator structure. However, no comparator structure that can meet all the requirements of medium/high resolution, high speed, and low power consumption is developed yet. The difficulty lies in that to fulfil the requirement of medium/high resolution, the input referred offset (also referred to as the offset voltage) produced by the comparator due to process mismatch has to be cancelled or calibrated to achieve a desired resolution. In existing offset calibration techniques, at least one preamplifier and/or one sampling capacitor have to be disposed on the input signal path of a comparator. However, since there is quiescent current consumption in the preamplifier, the signal bandwidth is affected and accordingly the surface area of the chip is increased.
In order to remove the preamplifier and/or sampling capacitor on the signal path, a technique is disclosed in the article titled “A 0.16 pJ/Conversion-Step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm Digital CMOS Process” published by Van der Plas in 2006 (IEEE ISSCC). According to this article, an offset voltage is first generated by using an imbalanced input pair and served as a reference voltage (i.e., coarse adjustment). Then, foreground offset calibration is performed on the offset voltage based on a concept of imbalanced output capacitor array, so as to obtain a desired reference voltage (i.e., fine adjustment).
Accordingly, in a fully differential application of the ADC disclosed by Van der Plas, the number of input pairs can be reduced from two to one since the reference voltage is built in the ADC. However, the disadvantages of the ADC disclosed by Van der Plas are that the coarse adjustment performed on the offset voltage is very sensitive to any process variation and the signal can only be adjusted within a very limited range. Besides, to achieve a higher resolution (>4 bits), the resolution of an output capacitor array for offset calibration has to be increased.
In addition, two comparator-related offset calibration techniques are disclosed in U.S. Pat. Nos. 7,405,682 and 6,320,426. Moreover, more comparator-related offset calibration techniques are disclosed in the article titled “Offset calibrating comparator array for 1.2-V, Gbit, 4-GSPs flash ADCs using 0.13 um generic CMOS technology” published by Hiroyuki Okada in 2003 at IEEE ESSCIRC, the article titled “A Low Power 6-bit Flash ADC with Reference Voltage and Common-Mode Calibration” published by Chun-Ying Chen in 2008 at the conference of IEEE Symposium on VLSI Circuits, the article titled “A 6-b 1-GSPs 30-mW ADC in 90-nm CMOS Technology” published by Yuan-Ching Lien in 2008 at IEEE A-SSCC, and the article titled “A 90 nm CMOS 1.2 V 6b 1 GS/s Two-Step Sub-ranging ADC” published by Pedro M. Figueiredo in 2006 at IEEE ISSCC.